Replacement gates are widely used in the manufacturing of integrated circuits. In the formation of replacement gates, polysilicon gates are formed first, and replaced by metal gates in subsequent process steps. With the using of replacement gates, the gates of PMOS and NMOS devices can have band-edge work functions, so that their performance can be optimized.
The replacement gates typically have great heights, and hence the aspect ratios of the gaps between gate stacks are also high. For example, FIG. 1 illustrates gate polys 102 and 104 adjacent to each other. Gap 106 is thus formed between gate polys 102 and 104. After the formation of gate polys 102 and 104, contact etch stop layer (CESL) 108 may be formed. The formation of CESL 108 adversely results in an increase in the aspect ratio of gap 106.
Referring to FIG. 2, inter-layer dielectric (ILD) 110, often referred to as ILD0, is formed to fill gap 106. In subsequent process steps, gate polys 102 and 104 may be replaced with metal gates. Currently, high-density plasma (HDP) processes are widely used for the ILD0 gap filling process. However, the gap filling capability of HDP is not satisfactory, and hence void 112 may be formed in gap 106. If formed using advanced technologies such as 22 nm or 20 nm technologies, the aspect ratio of gap 106 is particularly high. What is needed, therefore, is a method and structure for overcoming the above-described shortcomings in the prior art.